In structuring this book, the authora (TM)s hope was to provide interesting reading for a broad range of design automation readers. The first two chapters provide an overview of digital systems design and, in particular, verification. Chapter 3 reviews mainstream symbolic techniques in formal verification, dedicating most of its focus to symbolic simulation. The fourth chapter covers the necessary principles of parametric forms and disjoint-support decompositions. Chapters 5 and 6 focus on recent symbolic simulation techniques, and the final chapter addresses key topics needing further research.
Scalable Hardware Verification with Symbolic Simulation is for verification engineers and researchers in the design automation field.
Highlights:
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In structuring this book, the authora (TM)s hope was to provide interesting reading for a broad range of design automation readers. The first two chapters provide an overview of digital systems design and, in particular, verification. Chapter 3 reviews mainstream symbolic techniques in formal verification, dedicating most of its focus to symbolic simulation. The fourth chapter covers the necessary principles of parametric forms and disjoint-support decompositions. Chapters 5 and 6 focus on recent symbolic simulation techniques, and the final chapter addresses key topics needing further research.
Scalable Hardware Verification with Symbolic Simulation is for verification engineers and researchers in the design automation field.
Highlights:
Imprint | Springer-Verlag New York |
Country of origin | United States |
Release date | December 2005 |
Availability | Expected to ship within 10 - 15 working days |
First published | 2006 |
Authors | Valeria Bertacco |
Dimensions | 235 x 155 x 12mm (L x W x T) |
Format | Hardcover |
Pages | 180 |
Edition | 2006 ed. |
ISBN-13 | 978-0-387-24411-2 |
Barcode | 9780387244112 |
Categories | |
LSN | 0-387-24411-5 |