Power-Aware Testing and Test Strategies for Low Power Devices (Hardcover, 2010 ed.)


Managing the power consumption of circuits and systems is now considered one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as dynamic voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and EDA solutions for testing low power devices.


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Product Description

Managing the power consumption of circuits and systems is now considered one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as dynamic voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and EDA solutions for testing low power devices.

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Product Details

General

Imprint

Springer-Verlag New York

Country of origin

United States

Release date

November 2009

Availability

Expected to ship within 12 - 17 working days

First published

2010

Editors

, ,

Dimensions

235 x 155 x 22mm (L x W x T)

Format

Hardcover

Pages

363

Edition

2010 ed.

ISBN-13

978-1-4419-0927-5

Barcode

9781441909275

Categories

LSN

1-4419-0927-3



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