This self-contained book addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation.
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This self-contained book addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation.
Imprint | Springer-Verlag New York |
Country of origin | United States |
Release date | November 2010 |
Availability | Expected to ship within 10 - 15 working days |
First published | 2008 |
Authors | Saraju P. Mohanty, Nagarajan Ranganathan, Elias Kougianos, Priyardarsan Patra |
Dimensions | 235 x 155 x 17mm (L x W x T) |
Format | Paperback |
Pages | 302 |
Edition | Softcover reprint of hardcover 1st ed. 2008 |
ISBN-13 | 978-1-4419-4554-9 |
Barcode | 9781441945549 |
Categories | |
LSN | 1-4419-4554-7 |